Robustness of LDMOS power transistors in SOI-BCD processes andderivation of design rules using thermal simulation

摘要

In SOI devices, the buried oxide alters the thermal impedancecompared to a bulk device and a gives a higher temperature rise thatinfluences the robustness of the device. In this paper, power LDMOStransistors (with integrated temperature sensors) in an SOI-process areevaluated with Safe Operating Area (SOA) measurements. The failuremechanism based on triggering of the parasitic bipolar, is discussedwith the aid of dynamic temperature measurements. The results show thatthe failure energy can be related to a critical temperature rise thatdepends on V_DS. Consequently, the thermal impedance andV_DS fully determine the failure energy. Hence, 3D thermalsimulation can be used as a tool for dimensioning power transistors. Acomparison of SOI-DMOS with bulk-DMOS and bulk-Bipolar shows that in SOIit is still very well possible to create power devices with a good SOA