Design and simulation of a high performance rail-to-rail CMOS op-amp at /spl plusmn/3V supply

摘要

The paper discusses a CMOS operational amplifier at /spl plusmn/ 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V//spl mu/s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.