Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any high performance IC designs nowadays, however, buffer insertion has not gained enough attention in addressing this issue. In this paper, we propose a novel algorithm for buffer insertion to consider process variations. The major contribution of this work is two-fold: (1) an efficient technique to handle correlated process variations under nonlinear operations; (2) a provable transitive closure pruning rule that makes linear complexity variation-aware pruning possible. The proposed techniques enable an efficient implementation of variation-aware buffer insertion. Compared to an existing algorithm considering process variations, our algorithm achieves more than 25x speed-up. We also show that compared to the conventional deterministic approach, the proposed buffer insertion algorithm considering correlated process variationsimproves the parametric timing yield by more than 15%.
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