首页> 外文会议>Real Time and Embedded Technology and Applications Symposium, 2005. RTAS 2005. 11th IEEE >VPN gateways over network processors: implementation and evaluation
【24h】

VPN gateways over network processors: implementation and evaluation

机译:网络处理器上的VPN网关:实施和评估

获取原文

摘要

Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45 Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII 1 GHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.
机译:VPN和内容过滤等网络应用程序需要额外的计算能力,才能满足当今的吞吐量要求。除了纯ASIC解决方案之外,网络处理器体系结构还可以作为一种替代方案,在保持设计灵活性的同时扩大数据平面处理的规模。本文而不是提出新算法,而是说明了在网络处理器上开发基于IPSec的VPN网关的经验,并研究了性能问题。外部基准测试表明,使用3DES算法的系统可以达到IPSec的45 Mbps,与单个XScale核心处理器相比提高了350%,与PIII 1 GHz处理器的吞吐率相当。通过内部基准测试,我们分析了主要功能模块的周转时间,并将核心处理器确定为数据包转发和IPSec处理的性能瓶颈。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号