A 1.8 V 1.1 GHz novel digital multiplier

摘要

This paper presents the design of an 8 times 8-bit novel digital multiplier providing a better performance than the conventional linear array multipliers in two folds of speed and power consumption. The modified pairwise and parallel addition algorithms provide high speed multiplication in this work. The power performance of individual block is pre-evaluated to identify the most power consuming element and attempt is to select the most efficient topology to reduce the power consumption of entire multiplier while maintaining the high operating frequency. The proposed multiplier has been designed and implemented employing TSMC 0.18 mum CMOS technology and analyzed using HSPICE. When the multiplier is targeted to a maximum operating frequency of 1.1 GHz at V_DD equal to 1.8 V, it dissipates 22 mW. For comparison purposes a Baugh-Wooley multiplier is redesigned and optimized. The simulation results are compared showing superiority of proposed multiplier in both power and speed performance