This paper describes the design of a topology for array-structured (both Gate-Array and Polycell) semicustom LSI, in the context of a CMOS gate-array fabricated to test both the topology and the unique functional cells. Design emphasis has been placed on 100% routability, which is achieved by use of interdigitating cell terminals. Also described is the structure and operation of an automatic customisation software package which has been developed for the array, and which utilises the topological advantages to achieve track densities which are comparable with state-of-the-art algorithms. Examples are cited which show that this methodology is economical in both its speed of operation and its silicon-area utilisation.
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