首页> 外文会议>2005 IEEE Wireless Communications and Networking Conference >A Logic Design Front-End for Improved Engineering Productivity
【24h】

A Logic Design Front-End for Improved Engineering Productivity

机译:用于提高工程生产率的逻辑设计前端

获取原文

摘要

We have developed Design and Verification (DAV) as a new design front-end for the IBM Engineering Design System. DAV is a menu-driven system with powerful graphics capabilities for the entry and verification of a logic design. The design is hierarchically structured, using high-level technology-independent operators that can be simulated and verified at a purely logical level, then transformed into specific technologies and checked for LSSD rules and physical design constraints. The stated goals of DAV are for the product to get to the market in 30% less time, with 40% lower design cost, and with 98% percent of the errors removed prior to hardware prototyping. We expect to achieve these goals fully.
机译:我们已经将设计和验证(DAV)开发为IBM工程设计系统的新设计前端。 DAV是具有强大图形功能的菜单驱动系统,用于输入和验证逻辑设计。设计是分层结构的,使用与技术无关的高级运算符,可以在纯逻辑级别上进行仿真和验证,然后将其转换为特定的技术,并检查LSSD规则和物理设计约束。 DAV的既定目标是使产品在30%的时间内进入市场,降低40%的设计成本,并在硬件原型制作之前消除98%的错误。我们期望完全实现这些目标。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号