Automatic Placement Algorithms for High Packing density VLSI

摘要

Five placement procedures which combine three basic algorithms are developed and incorporated to our system. Evaluation of results is presented. Compared with manual design the optimum procedure reduces block size by 6.5%. The normalized area for one transistor (NA) is defined as the measure of automatic layout performance. NA is the product of wiring pitch. Optimum NA is confirmed to be 14.9 for manual design and 13.9 for automatic layout using the optimum procedure. This system is applicable to both custom logic LSIs and masterslice LSIs and has been applied to layouts of many such devices.