A programmable logic architecture for prototyping clockless circuits

摘要

This paper presents a novel programmable logic device (PLD) architecture for implementing and prototyping various styles of clockless or asynchronous circuits. Many classes of asynchronous circuits exist, depending on the timing assumptions that are made at the logical level and the adopted handshake communication protocols. The main objective of this work is to break the dependency between the PLD architecture dedicated to asynchronous logic and the logic style. Indeed, the PLDs dedicated to asynchronous logic are always style-oriented. The innovative aspects of this architecture are described in details. Moreover, the structure is well suited to be adapted with further asynchronous logic evolutions thanks to the architecture genericity. The programmable structure is flexible enough to be used with different logic styles and asynchronous design flows. As an example, a full-adder was implemented in two different styles of logic to demonstrate the PLD architecture flexibility. This work is included in a larger project called TAST, dedicated to the synthesis and the prototyping of multistyle logic asynchronous circuits.