There are a number of factors that motivate the use of hierarchical physical design approaches for ASIC and mircroprocessor designs. While microprocessor designs have traditionally been done using hierarchy, the trend in ASIC designs is more recent. The growing use of hierarchy presents new challenges to the design automation community. Tools and algorithms that are designed to work well on flat chips certainly can be applied to individual partitions of a hierarchical design. This works well for some tasks, but there are a host of new problems introduced by hierarchy boundaries that are not addressed by such an approach. This talk will focus on some of the new and interesting physical design automation tasks, with an emphasis on the placement and timing closure aspects of the hierarchy problem.
展开▼
