A clock frequency doubler using a passive integrator and emitter-coupled comparator circuit

摘要

A frequency doubler circuit is described using an integrator circuit, a comparator, and an exclusive OR (XOR) gate for use with clock waveforms. The integrator and comparator circuits delay the incoming signal by T/4 (90/spl deg/), where T is the clock period. When the delayed and the original signal enter the XOR gate, the output is a signal with twice the frequency of the clock. This circuit concept was verified experimentally using a 1 MHz input signal, which resulted in a 2 MHz output signal.