Analysis of delay caused by bridging faults in RLC interconnects

摘要

A novel technique to model resistive bridging defects in the presence of inductive and capacitive effects is described. It is well known that resistive bridges can degrade performance without resulting in logic errors-the focus of This work is on the analysis and computation of this extra switching delay caused by resistive bridging defects between interconnect lines. Through a series of transformations, a simple, highly accurate, and computationally efficient closed-form RLC model for resistive bridges between interconnect lines is developed. This single-stage RLC model can accommodate a resistive bridge at an arbitrary site between two interconnect lines. A full set of simulation results show that on average, the model is 25X faster and accurate to within 4% of the results obtained using a 20-stage distributed RLC interconnect model in SPICE.