The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

摘要

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.