Analog sampled data architecture for discrete Hartley transform for prime N

摘要

This paper describes an analog VLSI architecture, capable of computing discrete Hartley transform(DHT), for any prime N using standard analog blocks. The scheme operates from the general expression of DHT where the input samples are multiplied by all the DHT coefficients, simultaneously using an array of capacitors. These multiplied values are then switched concurrently with the help of cross point switch, to different integrators for performing necessary addition/subtraction. The proposed architecture is regular, simple to implement in VLSI and well suited where silicon area and power are to be minimized with some compromise on accuracy.