Low power high speed I/O interfaces in 0.18 /spl mu/m CMOS

摘要

The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 /spl mu/m CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.