From CSP to WLP

摘要

CSPs have been successfully introduced into the marketplace for mobile products. The CSP is basically a definition with respect to the package to die ratio and no new technology. In contrast manufacturing a CSP at wafer level requires new processes to achieve a sufficient reliability without underfilling at board level. A major goal for a wafer level package technology (WLP) with respect to single chip packaging is cost reduction because the WLP has to compete with the classic CSP. Within the European ESPRIT programme ESCHETA the Technical University of Berlin is developing a Wafer Level Package called S~3-Diepack. The S~3-Diepack uses stacked solder spheres and a solder support structure to improve the board level reliability without underfilling. The S~3-Diepack process has been applied to a test chip with a pitch of 0.4 mm for HF application. Board level reliability results are presented. Depending on the test conditions 750 up to 1000 cycles were passed before electrical failure and therefore the S~3-Diepack fulfils the requirement for consumer products. A cost model shows that the S~3-Diepack is an attractive solution.