A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization

摘要

Read channels for Hard Disk Drives (HDD) are a strategic business for many semiconductor companies. Many different factors contribute to the success of a HDD on the market, among which data rate, storage density, system complexity (i.e., area and power consumption) play a fundamental role. This work presents a new channel architecture based on Fractionally Spaced Equalization (FSE) on an EPR-IV pulse shape, that grants a significant system simplification compared to other standard architectures. The simplification comes from the reduced sensitivity of the FSE architecture to sampling phase and frequency errors, while the demand in terms of circuit bandwidth of the oversampled approach is eliminated thanks to a multirate structure. The equalizer is realized as an analog, sampled-data system with benefits in terms of pulse shaping precision, bandwidth tunability, frequency response programmability and ADC accuracy, which is reduced to two bits. The system has been designed at the circuit level in a 0.35 /spl mu/m standard CMOS technology for a 300 MHz channel. Simulations demonstrated a 700 mW power consumption at Bit Error Rate comparable with that of other standard solutions.