A parameterizable fault simulator for bridging faults

摘要

We present the concept of a multiple-valued logic simulator that is able to more accurately determine the possible behavior of a circuit in the presence of bridging faults. By a user defined mapping of a range of voltages to a logic value the simulator takes care of certain voltages more closely than common bridge fault simulators that map all voltages to either logic 1 or 0. Experimental results are given to demonstrate the improved fault detection possibilities.