Scaling transistor feature size allows greater density, higher performance and lower cost. The unrelenting pursuit of device scaling has enabled MOS gate dimensions to be reduced from 10/spl middot/m in the 1970's to a present day size of 0.1/spl middot/m. Conventional scaling of gate oxide thickness, source/drain extension, junction depths, and gate lengths have brought about several new technology issues invalidating some earlier methods for resting ICs. To enable testing devices into the 21/sup st/ century, new approaches are required in both test and design for testability. In this paper, we define the problems that arise with device scaling such as gate oxide leakage, subthreshold leakage, power density, electromigration, and soft error problems in qualitative and quantitative terms. The latter half of the paper deals with some of the solutions being pursued at Intel.
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