Efficient minarea retiming of large level-clocked circuits

摘要

Delay-constrained area optimization is an important step insynthesis of VLSI circuits. Minimum area (minarea) retiming is apowerful technique to solve this problem. The minarea retiming problemhas been formulated as a linear program; in this work we presenttechniques for reducing the size of this linear program and efficienttechniques for generating it. This results in an efficient minarearetiming method for large level-clocked circuits (with tens of thousandsof gates)