A VHDL-based methodology for top-down design, starting from an executable specification, supporting refinement towards RTL is proposed for the multimedia domain. The methodology is demonstrated using an MPEG-2 video decoder. A key idea for writing an initial executable specification is to keep the modeling style as close as possible to thinking in the domain. The executable specification is refined by partitioning the initially sequential model into concurrent processes and by moving functionality between blocks. During partitioning, control-dominated parts are separated from data-intensive calculations to enable domain-specific refinement. Finally the timing is refined from the causal to the clock-related level to enable performance simulation.
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