Access paths and testing in an ultra high-performance ATM switch

摘要

This paper discusses the architecture and testing of an ultra high performance 4-input, 4-output asynchronous transfer mode (ATM) switch that has been designed as part of the DARPA-sponsored "Thunder and Lightning" project at the University of California, Santa Barbara. This research project is focused on the design and prototype demonstration of ATM links and switches operating at or above 40 gigabits per second per link (TDM), with potential scalability to 100 Gbit/sec. Such aggressive link rates place severe requirements on switch architecture, particularly the buffering scheme. We discuss the access paths and test techniques used in the development and verification of this electronic ATM switch and describe reasons for the main design choices.