The impact of using the RISC architecture in the network nodes processor

摘要

The RISC architecture has many important features that make such an architecture very useful in the development of a network nodes processor. However, the use of a large number of registers in the RISC architecture has contributed to the increase in the context swapping processing overhead. Such overhead has been measured in this work and found to be significant, about 9.2% on average of the total signaling protocol processing, at the signaling nodes. The concept of non-overlapped multiple register sets (NMRS) is investigated in this work to reduce the processing overhead. The NMRS has supported four different strategies to allocate task context to its different sets. These four strategies: the least recently used; frequency; random; and priority, have been simulated and their impact on reducing the context swapping overhead has been evaluated. It is found that the contribution of these strategies to improve the NMRS performance is very small.