Practical sequential circuits are hard to test because they contain a large number of internal states that are difficult to control and observe. Scan design is often used to simplify testing; however, it is not always applicable because of area and performance penalties. Recent advances in sequential circuit testing have led to techniques and tools that provide test sets with high coverage of single stuckline (SSL) faults for non-scan circuits. However, these test sets contain a large number of patterns and require a tester with considerable pattern depth. We propose a novel method for encoding patterns such that the test set can be applied using low-cost testers that do not require excessive memory. We demonstrate the feasibility of our approach by applying it to SSL test sets for the ISCAS 89 benchmarks.
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