A novel approach for full digital modems implementing asynchronous sampling techniques

摘要

This article deals with full digital modem architectures, and more specifically with multirate demodulators. We aim at an overall complexity minimization of the receiver structure, by implementing a completely asynchronous sampling scheme, in conjunction with a single optimized filtering module, which carries out the intersymbol interference cancellation along with a specific interpolation algorithm. This allows one to decrease the oversampling ratio down to the theoretical bound, thereby restraining computational requirements, while reducing dramatically the traditional analog circuitry. Concretely, such a multirate demodulator should ultimately appear as a low-cost A/D converter operating at a unique sampling frequency, followed by an ASIC.