VLSI-Array Architecture for the Hierarchical BMA

摘要

In this paper VLSI-array architecture for the Hierarchical block-matching algorithm using a Mean Pyramid structure is presented. Due to the novel arrangement of data flow, we can map HBMA onto systolic array without hardware redundancy.The architecture can estimate motion vectors of 720×480 image with frame rate 30, for the displacement of -28 pixels, at 50MHz clock rate.We simulated the proposed architecture using Verilog-XL and synthesized it using Compass.Simulation results show that the architecture can be fabricated with the state-of-the-art CMOS technologies in one chip.