Design techniques that can improve the aliasing probabilities of signature circuits for VLSI BIST (built-in self-test) are presented. The proposed techniques are based on the binary weight distributions of error-correcting codes over GF(2) and GF(2/sup m/). The technique considered for calculating the aliasing probability of signature circuits is appropriate for a vector supercomputer. Some of the calculations were done using the S810 supercomputer. The vectorization ratio of the program was 99.885% for an MISR (multiple-input signature register) with 16 inputs and for test length n=100-105.
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机译：提出了可以提高VLSI BIST（内置自检）签名电路的混叠概率的设计技术。所提出的技术是基于GF（2）和GF（2 / sup m /）上的纠错码的二进制权重分布。考虑用于计算签名电路的混叠概率的技术适用于矢量超级计算机。一些计算是使用S810超级计算机完成的。对于具有16个输入且测试长度为n = 100-105的MISR（多输入签名寄存器），程序的矢量化率为99.885％。
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