An algorithmic analog-to-digital converter using unity-gain buffers

摘要

An algorithmic stage for bipolar 1-b analog-to-digital (A/D) conversion using a unity-gain buffer is proposed. Cyclic and pipeline A/D converter architectures using this stage iteratively or in cascade are also described. Error analysis and SPICE simulations show that a conversion accuracy higher than 8 b and a conversion rate up to 10 Mb/s are attainable with presently available 3- mu m CMOS technologies. Videofrequency operation may also be possible with finer linewidths. The component requirement is minimal, and thus it is best suited for an analog interface in application-specific integrated circuits. A prototype converter built using discrete components has confirmed the principles of operation.