Level-Crossing Detection based Low-Power Sigma-Delta ADC for Sensor Applications

摘要

A Current Controlled Oscillator (ICO), integrates its information-bearing current-input-signal iin using a capacitor, C. The voltage VC across C, namely the integral, is reset or folded when it reaches a level VREF. If iin (dq/dt) is constant, then VC is a saw-tooth waveform. Since the frequency of the oscillator is defined as the rate of change of phase, the phase wraps itself after every 2π radians or its corresponding voltage VREF. With this property we propose an open-loop continuous-time Sigma-Delta ADC combining level-crossing detection and folding techniques using an ICO. We also propose a technique to increase the effective resolution of the ADC by inserting additional voltage-levels for detection between 0 and VREF. The complete ADC is designed in TSMC 40nm CMOS technology. The simulation results show an ENOB of 12.2-bits consuming 1.5μW of power from a 1V supply corresponding to a Schreier-FOM of 167.2dB and a Walden-FOM of 157fJ per conversion cycle.