A Defective Level Monitor of Open Defects in 3D ICs with a Comparator of Offset Cancellation Type

摘要

Resistive open defects in 3D ICs may change into hard open ones that cause logical errors after shipping to a market. In this paper, a built-in defective level monitoring circuit is proposed to monitor the changing process of resistive open defects occurring at interconnects among dies of 3D ICs in a market. The defect level of a resistive open defect is monitored by means of quiescent supply current made flow with an IEEE 1149.1 test circuit embedded inside dies in the ICs. The monitoring circuit consists of an I-V converter and a comparator of offset cancellation type. Feasibility of the process monitoring is examined by SPICE simulation in this paper. It is shown that the changing process of a resistive open defect can be monitored at the sensitivity of 5Ω.