A Self-Protected 800V JFET with 6kV HBM robustness in 0.25 um BCD

摘要

A novel device architecture is introduced that enables 6kV HBM self-protection in 800V JFET transistors. The proposed solution is realized without any additional processing or masking steps. The physics behind this ESD protection scheme is explained. A side-by-side comparison is done to compare the ESD performance between the new device and the conventional one based on Silicon measurement results.