Nanosecond (NLA) laser annealing is under consideration for inclusion into mainstream CMOS technology. Lack of suitable ultra-high speed pyrometery and the complexity of determining surface temperature of patterned, nanostructured wafers poses unique challenges in tool monitoring and process setup. This work sets a methodology of calibrating the incident energy density (ED) at the wafer plane and the surface temperature for blanket and pattern wafers. The melting of undoped crystalline silicon (c-Si) at 141°C and that of the transistor channel were used as reference points for blanket and patterned wafers, respectively. Laser-induced epitaxial re-growth of amorphized layers and pockets and the melting of the pFET SiGe source/drain (S/D) were used to show consistency between the calibrated incident ED and predicted surface temperature. This methodology allows for reliable annealing process setup and adequate periodic tool monitoring and matching.
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