Implement of Two New High-Speed Low-Power PFDs with Low Blind Zone and Dead Zone in 65nm CMOS Technology

摘要

In this paper, two new low-power high-speed symmetric phase-frequency detectors (PFDs) are presented: an open-loop PFD, and a closed-loop PFD. Based on the new structures, a very low dead zone and blind zone operation are achieved. The proposed structures are simulated in the TSMC 65 nm CMOS process with a 1.2 supply voltage. The post layout simulation results demonstrate that the open-loop and closed-loop PFD can operate up to 16.67 GHz and 7 GHz, respectively, while the detection range for both structures is ±2π. Moreover, the dead zone of 2.5 ps and 5 ps is attained for the open-loop and closed-loop structures, respectively. Also, layout sizes of the open-loop and closed-loop PFDs are 360 $mu mathrm{m}^{2}(20mu mathrm{m}imes 18mu mathrm{m})$ and 233.5 $mu mathrm{m}^{2}(16.1mu mathrm{m}imes 14.5mu mathrm{m})$, respectively. Therefore, both of proposed PFDs are good candidates to provide phase-locked loop (PLL) functions with a low circuit intricacy and low jitter.