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Efficient Implementation of Concurrent Lookahead Decision Feedback Equalizer using Offset Binary Coding

机译:使用偏移二进制编码有效地实现并发保护判决反馈均衡器

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In this paper, an efficient implementation of the concurrent decision feedback equalizer (DFE) is carried out using offset binary coding (OBC) based on distributed arithmetic (DA). The concurrent decision feedback equalizer is employed in multi-gigabit systems which uses the principle of parallelization. However, the hardware complexity of adders and multipliers rises quadratically with parallelization factor. In our proposed technique, we have used look-up table (LUT) and shift-accumulate block as per DA requirement. In order to reduce the access time of LUT, we employed OBC scheme which therefore improves the speed of filtering operation. Moreover, it also reduces the chip area for LUT based filter design. Furthermore, our design provides significant reduction of hardware complexities in spite of slight increase in address decoding logic of OBC combinations while LUT complexity grows linearly. By doing so, the concurrent nature of look-ahead DFE is unaltered and can still be used for multi-gigabit applications. We have estimated hardware complexity and critical path of our design and compared with best existing schemes. Synthesis is performed in UMC 180 nm CMOS technology using cadence RTL compiler for the feedback filter length N = 4, 6 and 8. The proposed structure of concurrent look-ahead DFE is found to have low area in comparison to other schemes for any length of the feedback filter.
机译:在本文中,基于分布式算术(DA),使用偏移二进制编码(OBC)来执行并发判定反馈均衡器(DFE)的有效实现。并发判定反馈均衡器在多千兆位系统中使用,该系统使用并行化原理。然而,加法器和乘法器的硬件复杂性与并行化因子相当地升高。在我们提出的技术中,我们使用了根据DA要求使用查找表(LUT)和移位累积块。为了减少LUT的访问时间,我们采用了OBC方案,从而提高了过滤操作的速度。此外,它还减少了基于LUT基于滤波器设计的芯片区域。此外,尽管OBC组合的地址解码逻辑略微增加,但随着OBC组合的略微增加,我们的设计可以显着降低硬件复杂性。通过这样做,展开的远程DFE的并发性质不妨碍,仍可用于多千兆应用程序。我们估计了我们设计的硬件复杂性和关键路径,并与最佳现有计划进行了比较。使用CAdence RTL编译器在UMC 180nm CMOS技术中进行合成,用于反馈滤波器长度n = 4,6和8.发现与任何长度的其他方案相比,发现了并发远程DFE的所提出的结构。反馈过滤器。

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