Optimization of QPSK MODEM with A WGN Implemented in FPGA

摘要

This paper proposes a Quadrature Phase Shift Keying (QPSK) using three different methods. QPSK is one of the forms of Phase Shift Keying (PSK) modulation scheme. Generally a conventional QPSK modulator with Direct Digital Synthesizer (DDS) and arithmetic multiplier separates base band signal into I and Q phase which consumes low throughput with complexity in hardware implementation. Hence to generate high throughput QPSK modulator, the first proposal uses an up and down accumulator for carrier generator instead of DDS and arithmetic multiplier is modified as BOOTH multiplier. The second proposed method will produce the QPSK signal which is based on stored QPSK phase data in ROM which eliminates completely the DDS and multiplier blocks of the modulator. In proposed method-3 the modulator is designed by using Vedic multiplier and carry look-ahead adder(CLA) and demodulator is designed using FIR Low Pass Filter with additive white Gaussian noise (AWGN). FIR low Pass filter coefficients are generated in MATLAB using rectangular window and hamming window. The whole system has been simulated in Xilinx 14.7 and successfully downloaded on to the Field Programmable Gate Array (FPGA) chip XC3S400-4pq208 and XC6SLX45 - CSG324. The result shows that the proposed methods can greatly improved the speed and reduced the latency and gives better frequency of operation.