Low Latency and Area Efficient VLSI Architecture of 2D Bilinear Interpolation using Brent Kung Adder Based Fast Multiplier

摘要

Real-time image processing has extended its applicability that includes significant domains like satellite imaging and medical imaging. Despite such massive usage, the prospect of real-time imaging throttles due to the scarcity of any dedicated hardware. The dearth of any available VLSI architectures for real-time imaging can be attributed to the computational loads of the imaging methods. The 2D bilinear interpolation is an important operation extensively utilized in image scaling, image inpainting, and also in the post-processing step of image registration. But there hardly exists any suitable hardware for real-time image interpolation. In this paper, an innovative first-of-its-kind VLSI architecture for 2D bilinear interpolation has been presented. Our proposed pipelined VLSI architecture is based on our proposed shift and adds based multiplier, which is mostly combinational. In our proposed multiplier, we have used brent kung adder, which is popular for its fast computation. Our proposed architecture 2D bilinear interpolation consists of only some adders, hard shifters, and negligible numbers of logic gates. The presented design is also time-efficient, in the sense, the critical path delay is only restricted by the propagation delay of an adder, thereby ensuring the satisfactory value of maximum operating frequency. As the design is made pipelined, naturally, the throughput rate is high. The power efficiency of our proposed design is quite natural as the design contains only a few basic combinational modules along with some logic gates. The proposed design is realized using verilog before being simulated using the Xilinx Vivado 1S.2 tool. The simulated design is implemented in the FPGA of the Zynq UltraScale+ MPSoC evaluation board for verifying its quality in case of real-time applications. The simulated results and the outcomes of the real-time onboard testing confirm our claim of hardware, time, and power efficiency.