On the Development of the Compiler from C to the Processor with FPGA Accelerator

摘要

This work describes the further development of the compiler project for CPU with FPGA-accelerator. This compiler is based on the Optimizing Parallelizing System (OPS) of the Southern Federal University. There is a structure of the considered compiler briefly described in the article. Some specific parts of OPS internal representation for pipelines and automats to control pipelines are described in more detail. Examples of programs that are compiled by an experimental compiler are given, as well as high-level program transformations of OPS that can be used in this compiler.