Elevating Low-Quality Silicon Wafers For High-Efficiency Silicon Heterojunction Solar Cell Applications

摘要

We present defect-engineering approaches such as gettering and hydrogenation for silicon heterojunction structures. A method to evaluate the impact on the potential implied open circuit voltages of lifetime test structures is discussed. Lifetime analysis is performed on samples with silicon nitride passivation after defect-engineering to determine the injection level dependent bulk lifetime and dark saturation current density components. An implied open circuit voltage is predicted by assuming a dark saturation current density (J_0e) appropriate for the silicon heterojunction structure while accounting for the measured bulk lifetime of the material. Agreement within 5 mV is observed for the validation samples. Subsequently, the technique is used to assess the impact of defect engineering on the potential implied open circuit voltage of a range of samples. We show that treated wafers are expected to have improvement in implied open-circuit voltages of from 706 mV to 730 mV for n-type Cz-Si, 625 mV to 723 mV for p-type Cz-Si, from 677 mV to 714 mV for p-type mc-Si, and from 657mV to 692 mV for p-type UMG silicon wafers.