Collaborative Implementation of Hardware-Oriented GBDT Compress Algorithm Based on DSP+FPGA

摘要

GBDT (Gradient Boosting Decision Tree) is an algorithm that builds multiple decision trees by iteratively updating. Due to its strong generalization ability and fast operation speed, it is widely used in the realization of classification and regression. However, the GBDT classification model occupies large storage resources; its application on the mobile multimedia platform is greatly limited. To solve this problem, we come up with a new GBDT compression algorithm for hardware implementation [1]. And based on this algorithm, we designed a DSP+FPGA system to achieve four classifications of six-dimensional samples. DSP is responsible for classification control, while the FPGA implements the classification calculation process. This classification system not only occupies small hardware resources but also guarantee accuracy and speed.