Power optimization for FPRM logic using approximate computing technique

摘要

A power optimization algorithm based on approximate computing technique was proposed for FPRM logic circuits. The algorithm includes FPRM logic circuits dynamic power estimation model based on signal probability and transition density, a genetic algorithm for RM logic power optimization using polarity searching and error rate (ER) calculation for RM logic using double sharp product operation. Under the constraint of ER, some product terms are selectively deleted to reduce power consumption. The proposed algorithm is implemented in C and tested under MCNC benchmarks. Experimental results show that by using the approximate computing technique, the average dynamic power can be reduced by 22.77% with the average ER of 3.21%.