FPGA Implementation of All Digital Phase Locked Loop for ADC Synchronization with the Mains Frequency

摘要

One of the most accurate Analog-to-Digital converters are those of the integrating type. Their measurement speed is low but they have high precision. One of the important features in the laboratory environment is the ability to suppress the mains frequency interference signals. If the first integration phase is with period multiple of the mains period the interference is completely suppressed. A completely digital Phase Locked Loop is designed to provide the converter with clock frequency exactly multiple of the mains frequency. The whole system is implemented on FPGA programmable logic device.