Proposed Pipeline Clocking Scheme for Microarchitecture Data Propagation Delay Minimization

摘要

With the pipeline design, high data throughput is obtained. A pipeline works like an assembly line, before the prior data has finished, the new data can be processed. The core elements of the pipeline system are the flip-flops, and those flip-flops form the registers for the pipeline stages. In this paper, a proposed pipeline scheme is presented to avoid the halfway situation or unpredictable state due to the effect of flip-flops setup and hold times. A comparison with other pipeline schemes with respect to data propagation delay is also present. Conventional pipeline, wave pipeline and mesochronous pipeline systems are compared with the proposed pipeline system. The comparison process is considered with input pulses in the frequency range of 5 Hz-999 MHz and for three and four pipeline stages. The proposed pipeline system gives the best data propagation delay among the systems when the logic is introduced.