Modeling and analysis of DLLs for locking and jitter based on Simulink

摘要

This paper presents a behavioral modeling and simulation for delay-locked loops (DLLs) based on MATLAB Simulink. The fast locking time and output jitter performance of DLLs are analyzed in the model. Through systematical simulation in MATLAB Simulink, it can be achieved that the locking time is determined by current of Charge pump and filter capacitor. This paper introduces the equations related to output jitter from noise sources (input reference clock, phase frequency detector, charge pump and voltage-controlled delay line) for stage numbers, loop bandwidth, noise intensity and reset time. Furthermore the model is applied to verify these equations for analyzing output jitter and provides the design considerations for optimizing circuit performance.