A Triple Cross Coupled Down-Conversion Mixer in 65 nm CMOS technology

摘要

A 2.4 GHz folded mixer using 65 nm CMOS technology is presented in this paper. A triple cross-coupling technique is adopted to achieve low noise and high gain performance. Besides that, the transconductance stage are biased in subthreshold mode to further lower the power consumption of the architecture. This mixer exhibits a good conversion gain of about 18.28 dB with low power consumption of 0.82 mW from a 800 mV power supply. The noise figure is simulated to be 12.88 dB at 100 MHz IF frequency and the IIP3 is -6.562 dBm. This low power design is well adopted for Internet of Things (IoT) applications.