Development of FPGA based Hardware-in-the-loop Simulator for RF Cavity Resonator

摘要

This paper presents implementation of a Field Programmable Gate Array (FPGA) emulator for the Low Level Radio Frequency (LLRF) Normal conducting cavity at TRIUMF. Testing waveforms such as phase and amplitude in the cavity on the real hardware can be both difficult and dangerous. To allow testing of the real LLRF system in real time and also to obtain shorter processing time we need to have an effective hardware in the loop simulator of the cavity. Radio frequency(RF) cavity is equivalent to an electrical RLC circuit which acts like a second order filter model, therefore it is possible to emulate the cavity with an analog filter. But when it comes to digital field, the finite word length effect has to be considered and processed carefully. The discrete model of the cavity designed as an IIR bandpass Filter. The SIMULINK and MATLAB model of the cavity and their implementation are presented. An Altera DE4 development board was selected as the emulator of the cavity. And the result of digital designing of the cavity model on FPGA is presented.