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A Cortex-M3 Based MCU Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16 Power Variation Across Process and Temperature

机译:基于Cortex-M3的MCU,具有34NW静态电源的AVS,15.3pj / Inst。活性能量,工艺和温度的动力变化16%

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Power and energy efficiency poses a prime constraint on IoT SoCs. Dynamic voltage and frequency scaling (DVFS) - in combination with adaptive voltage scaling (AVS) - can trade performance for power matching the workload. However, classic timing closure leads to substantial power variations across process and temperature, especially from SS/Cold to FF/Hot due to leakage. This paper presents an ARM Cortex-M3 based MCU with integrated voltage regulator featuring AVS, which achieves for the CPU incl. 8kB SRAM 34nW static power, 15.3pJ/instruction active energy and 16% power variations across process and temperature (-40-120°C) corners measured in silicon. The digital subsystem employs a new replica scheme combining replica circuits and in-situ monitors to track critical paths under the inter/intra-die variations. Mandating AVS, we show a novel methodology for logic synthesis with optimal usage percentage per Vth level, at which point the power consumption is balanced and minimized across process and temperature.
机译:功率和能效对IOT SoC的主要约束。动态电压和频率缩放(DVFS) - 与自适应电压缩放(AVS)相结合 - 可以进行功率匹配工作负载的交易性能。然而,经典时序闭合导致过程和温度的大量功率变化,特别是由于泄漏而从SS / COV到FF /热。本文介绍了一个基于ARM Cortex-M3的MCU,具有AVS的集成电压稳压器,可用于CPU的AVS。 8KB SRAM 34NW静电,15.3pj /指令有源能量和16%的过程和温度(-40-120°C)硅的功率变化(-40-120°C)硅。数字子系统采用新的复制方案组合复制电路和原位监视器来跟踪在帧间/内模帧内的关键路径。授权AVS,我们为逻辑合成显示了一种新的方法,最佳使用百分比每V th 水平,此时功耗平衡并最小化跨处理和温度。

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