A Novel Content Addressable Memory Based on Hybrid Memristor-CMOS Architecture

摘要

In this paper, we proposed a novel design of binary content addressable memory (CAM) based on 1 transistor and 2 memristors (1 T2M) structures. In each cell, 2 memristors in series that stored complementary resistance states construct the memory part and the 1 transistor is used as access device. The proposed CAM has a simple structure, nanosecond search delays and low power consumption. The correctness and effectiveness of this design is verified by Hspice. Influences of different features like the counts of mismatch bits, transistor sizes and word length are also considered.