Resolving Loop Pipelining Issues in the CCC High-level Synthesis E-CAD Framework

摘要

Academic High-level Synthesis tools like CustomCoprocessorsCompiler have recently evolved in new versions with expanded functionality and more aggressive optimization schemes in order to satisfy hardware implementation requirements. Meanwhile, commercial tools like Xilinx VivadoHLS or, more recently, Compiler-driven code optimizations, are a useful means to improve quality of automatically generated hardware implementations. Such optimizations include loop transformations. Some of the most important transformations are loop unrolling and loop pipelining, which when they are combined with careful instruction reordering, deliver highly optimized schedules. Amongst others, instruction dependencies are significant limitations in loop optimization. In this paper, we discuss possible resolutions of loop pipelining issues such as dealing with dependencies between loop body operations. This has a great impact on high-level synthesis. Results from experiments with several benchmarks on the CustomCoprocessorsCompiler and VivadoHLS tools demonstrate that CustomCoprocessorsCompiler can deliver better output than VivadoHLS.