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EUV Capping Layer Integrity

机译:EUV封盖层完整性

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The era of EUV technology is approaching and use of EUV lithography in chip manufacturing process was reported. The EUV technology has still serious challenges to overcome, to which belong defectivity, source power and throughput of the exposure tool, to name the most obvious. Important part of the lithography, which differs significantly from previous optical technology, is the mask. The mask stack, especially the multilayer (ML) mirror surface and its protection is of high importance, determining the reflectivity of the mask. The ML mirror is protected by a thin Ru capping layer, which however is very sensitive to oxidation and damage during mask manufacturing processes and its use. Also estimation of the capping layer thickness is not trivial, and is unreliable by damage free analytical methods. In our work, we focus on the capping layer integrity and assess it as function of several applied cleaning processes. The integrity is examined via e-beam repair process and AFM measurement of the feature height. As identified in previous experiments, the UV exposure used in manufacturing processes has significant influence on the Ru layer at some conditions. However, there is good chance to find conditions at which the Ru layer is not attacked by the UV exposure, and removed by the subsequent wet process in which the products of Ru oxidization are diluted. Above mentioned procedure we intend to identify EUV mask manufacturing conditions, at which the capping layer is not impacted by the clean process. At the end of the manufacturing process, the EUV mask has to have a thick enough capping layer to perform the repair process and protect the ML mirror during the mask lifetime. Currently available processes allow us to manufacture EUV masks with a remaining capping layer up to five times thicker than required for the e-beam mask repair. This result confirms readiness of the mask manufacturing process for HVM from perspective of the mask health and integrity of the ML mirror and Ru capping layer.
机译:EUV技术的时代日益临近,据报道,EUV光刻技术已在芯片制造过程中使用。 EUV技术仍需克服严峻的挑战,其中最明显的就是缺陷率,源功率和曝光工具的吞吐量。光刻的重要部分是掩模,它与以前的光学技术有很大不同。掩模叠层,尤其是多层(ML)镜面及其保护非常重要,它决定了掩模的反射率。 ML反射镜由薄的Ru覆盖层保护,但是该覆盖层对掩模制造过程及其使用过程中的氧化和损坏非常敏感。另外,覆盖层厚度的估计也不是简单的,并且通过无损伤的分析方法是不可靠的。在我们的工作中,我们专注于覆盖层的完整性,并根据几种应用的清洁工艺对其进行评估。通过电子束修复过程和特征高度的AFM测量来检查完整性。如先前的实验所确定的,在某些条件下,制造过程中使用的紫外线暴露会对Ru层产生重大影响。然而,有很好的机会找到条件,在该条件下,Ru层不会受到紫外线照射的侵蚀,而会被随后的湿法工艺除去,在该工艺中,Ru氧化产物被稀释。上面提到的过程我们打算确定EUV掩模的制造条件,在该条件下,覆盖层不受清洁工艺的影响。在制造过程结束时,EUV掩模必须具有足够厚的覆盖层,以执行修复过程并在掩模寿命期间保护ML镜。当前可用的工艺使我们能够制造出EUV掩模,其剩余的覆盖层的厚度比电子束掩模修复所需的厚度厚五倍。从掩模健康状况以及ML镜和Ru覆盖层的完整性的角度来看,该结果证实了用于HVM的掩模制造工艺的准备就绪。

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