A Novel Half-Rate Dual-Response Phase Detector Implementation for a 25-28.3 Gb/s Clock and Data Recovery Circuit

摘要

The implementation of a novel half-rate dual-response phase detector, generating both linear and binary responses concurrently, is presented. Processing both binary and linear responses to drive a single on-chip voltage-controlled oscillator (VCO), lower jitter generation and higher jitter tolerance are attained simultaneously, providing a superior jitter performance. The phase detector is measured in a 25-28.3 Gb/s clock and data recovery (CDR) circuit with 7.75ps peak-to-peak total jitter at 1.0E-12 bit error rate (BER). The jitter tolerance is twice better than the optical module required tolerance mask over the entire frequency range. The chip is fabricated in 200GHz/280GHz (f_T/f_MAX) IBM 8HP 0.13μm SiGe BiCMOS process.